Good but not great
Good but not great
It has good benefits, like a good health care plan, PTO, and sabbatical, etc. Your work environment depends on your manager and team.
The projects get scrapped quite a few times, and there is no stability in upper management.
They are always reorganizing BUs, there's a power struggle, and they don't commit to great ideas, leaving them halfway into execution.
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Intel Interview Questions
Intel Interview Experiences
Design Verification Engineer
You will need good digital system experience, including state machines, logic gates, and programming. The language used is Verilog. Be prepared to discuss your previous projects. You should promote your technical capabilities and demonstrate a posit
Design Verification Engineer
They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow. Then questions were on the digital domain. Questions on Verilog and C/C++: * STA * Verilog project
Design Verification Engineer
Contacted by a recruiter. Went through: * Two rounds of technical phone interviews (1 on 1 with an engineer) * One round of on-site interview with the extended team.
Design Verification Engineer
MalaysiaDecember 30, 2024You will need good digital system experience, including state machines, logic gates, and programming. The language used is Verilog. Be prepared to discuss your previous projects. You should promote your technical capabilities and demonstrate a posit
Design Verification Engineer
Bengaluru, Karnataka, IndiaAugust 1, 2024They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow. Then questions were on the digital domain. Questions on Verilog and C/C++: * STA * Verilog project
Design Verification Engineer
United StatesMay 21, 2024Contacted by a recruiter. Went through: * Two rounds of technical phone interviews (1 on 1 with an engineer) * One round of on-site interview with the extended team.
