Work-life balance is great.
Not great pay, and the project gets boring.
There was an initial 30-minute call with the director, and then I was scheduled for a 1-hour call with the manager. The manager was in no mood to take the interview. Terrible experience.
You will need good digital system experience, including state machines, logic gates, and programming. The language used is Verilog. Be prepared to discuss your previous projects. You should promote your technical capabilities and demonstrate a posit
They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow. Then questions were on the digital domain. Questions on Verilog and C/C++: * STA * Verilog project
There was an initial 30-minute call with the director, and then I was scheduled for a 1-hour call with the manager. The manager was in no mood to take the interview. Terrible experience.
You will need good digital system experience, including state machines, logic gates, and programming. The language used is Verilog. Be prepared to discuss your previous projects. You should promote your technical capabilities and demonstrate a posit
They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow. Then questions were on the digital domain. Questions on Verilog and C/C++: * STA * Verilog project