Great Place, Good Team
Great Place, Good Team
Great place to work, good team.
None of them to mention.
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Intel Interview Questions
Intel Interview Experiences
Design Verification Engineer
There was an initial 30-minute call with the director, and then I was scheduled for a 1-hour call with the manager. The manager was in no mood to take the interview. Terrible experience.
Design Verification Engineer
You will need good digital system experience, including state machines, logic gates, and programming. The language used is Verilog. Be prepared to discuss your previous projects. You should promote your technical capabilities and demonstrate a posit
Design Verification Engineer
They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow. Then questions were on the digital domain. Questions on Verilog and C/C++: * STA * Verilog project
Design Verification Engineer
Santa Clara, California, United StatesApril 4, 2024There was an initial 30-minute call with the director, and then I was scheduled for a 1-hour call with the manager. The manager was in no mood to take the interview. Terrible experience.
Design Verification Engineer
MalaysiaDecember 30, 2024You will need good digital system experience, including state machines, logic gates, and programming. The language used is Verilog. Be prepared to discuss your previous projects. You should promote your technical capabilities and demonstrate a posit
Design Verification Engineer
Bengaluru, Karnataka, IndiaAugust 1, 2024They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow. Then questions were on the digital domain. Questions on Verilog and C/C++: * STA * Verilog project
