Good Balance, Bad Intel Politics
Good Balance, Bad Intel Politics
Good for work-life balance.
A lot of politics and redundant bureaucracy at Intel. They happily get rid of worker bees just to keep their cushy roles.
same as the cons
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Intel Interview Questions
Intel Interview Experiences
Post Silicon Validation Engineer
The interview took place from 9 AM to 3 PM. I had lunch with recruiters. The questions covered: * Computer architecture * Assembly languages (8086) * C language (linked lists and pointers) * Low power VLSI * Questions related to my projects and the
Post Silicon Validation Engineer
The interview included very rigorous, technical, problem-solving, and some behavioral questions. The overall difficulty was high but not tough. The interviewer was very knowledgeable and made me feel at ease. The focus was mostly on technical aspects
Post Silicon Validation Engineer
It was offline for 4 rounds of interviews. In the first round, they asked about the basics of Digital Electronics, such as: * Drawing a half-adder and full-adder circuit. * Designing an SR latch. * Drawing a 3-bit counter.
Post Silicon Validation Engineer
Austin, Texas, United StatesOctober 28, 2012The interview took place from 9 AM to 3 PM. I had lunch with recruiters. The questions covered: * Computer architecture * Assembly languages (8086) * C language (linked lists and pointers) * Low power VLSI * Questions related to my projects and the
Post Silicon Validation Engineer
United StatesJanuary 9, 2023The interview included very rigorous, technical, problem-solving, and some behavioral questions. The overall difficulty was high but not tough. The interviewer was very knowledgeable and made me feel at ease. The focus was mostly on technical aspects
Post Silicon Validation Engineer
Bengaluru, Karnataka, IndiaOctober 28, 2024It was offline for 4 rounds of interviews. In the first round, they asked about the basics of Digital Electronics, such as: * Drawing a half-adder and full-adder circuit. * Designing an SR latch. * Drawing a 3-bit counter.
