Great place to develop technical skills. Bad place if you are an aggressive person
Great place to develop technical skills. Bad place if you are an aggressive person
Really good working culture, but this depends on your manager.
Very slow promotion, especially during the pandemic.
No bonus and low increment.
Giving more opportunities not just for technical improvement, but for increment and bonus.
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Intel Interview Experiences
Pre-Silicon Validation and Verification Engineer
The interview consisted of behavioral and technical portions. I didn't apply for this position initially, but after the interview, they asked me if I wanted to apply. The manager and engineers were nice and knowledgeable. The exciting part was tal
Pre-Silicon Validation and Verification Engineer
The interview consisted of two rounds. The first round was a screening. The second round was an advanced level, explaining a specific scenario for identifying test cases for new modifications in the existing design.
Pre-Silicon Validation and Verification Engineer
There are 2 rounds of technical interviews, each lasting 2 hours. Most of the questions they ask are from SystemVerilog (SV) and UVM, as well as from the project you are currently working on in your current organization.
Pre-Silicon Validation and Verification Engineer
United StatesNovember 1, 2015The interview consisted of behavioral and technical portions. I didn't apply for this position initially, but after the interview, they asked me if I wanted to apply. The manager and engineers were nice and knowledgeable. The exciting part was tal
Pre-Silicon Validation and Verification Engineer
United StatesMarch 1, 2022The interview consisted of two rounds. The first round was a screening. The second round was an advanced level, explaining a specific scenario for identifying test cases for new modifications in the existing design.
Pre-Silicon Validation and Verification Engineer
IndiaJanuary 7, 2021There are 2 rounds of technical interviews, each lasting 2 hours. Most of the questions they ask are from SystemVerilog (SV) and UVM, as well as from the project you are currently working on in your current organization.
