Great place to work
Great place to work
Wide variety of experience:
- CPU & SoC Design, verification, and post-silicon debug
Talented workforce, great building and facilities.
Bureaucratic processes and related inefficiencies. High degree of internal competition for good quality work.
Cut down inefficiencies. Do more with less.
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Intel Interview Questions
Intel Interview Experiences
Senior Staff Engineer
The process was quick and straightforward, involving interviews with just a couple of people. It was a good opportunity to learn about the company and ask questions. The interviewers were nice and helped foster a comfortable environment. The questi
Senior Staff Engineer
The interview was lengthy, with numerous stages and deep, widely diverse technical questions. I was contacted via email and arranged for a phone interview. The manager then took me and his team to lunch for further discussion and technical question
Senior Staff Engineer
The entire interview process was very friendly, especially the hiring manager. I had a one-hour phone screening interview, followed by a full panel on-site. I was asked to write some SystemVerilog code and was questioned on cache coherency protocol
Senior Staff Engineer
Albuquerque, New Mexico, United StatesSeptember 15, 2023The process was quick and straightforward, involving interviews with just a couple of people. It was a good opportunity to learn about the company and ask questions. The interviewers were nice and helped foster a comfortable environment. The questi
Senior Staff Engineer
Chandler, Arizona, United StatesMay 1, 2016The interview was lengthy, with numerous stages and deep, widely diverse technical questions. I was contacted via email and arranged for a phone interview. The manager then took me and his team to lunch for further discussion and technical question
Senior Staff Engineer
Irvine, California, United StatesOctober 23, 2022The entire interview process was very friendly, especially the hiring manager. I had a one-hour phone screening interview, followed by a full panel on-site. I was asked to write some SystemVerilog code and was questioned on cache coherency protocol
