Smart Team, Chaotic Dev
Smart Team, Chaotic Dev
Had the opportunity to work with really smart individuals.
Too many changes all the time. Development and testing of software is done all over the place. In order to get things done takes too much time.
Stop re-organizing all the time.
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Intel Interview Questions
Intel Interview Experiences
Machine Learning Engineer
First, I have an interview with the team manager. After I pass the first interview, the technical interview follows. This interview takes 2 hours and the questions are mostly about the basic concepts of machine learning and deep learning. Then, I'm
Software Engineer
Flew out to the site and spent a day interviewing. Had four one-hour interviews. The people were very nice. The interviews were difficult, primarily because so much time was spent on them, and it was exhausting. Additionally, there was lunch with t
FPGA Simulation Verification
1 screening - 5 onsite rounds. Tested on SystemVerilog. * Write FIFO logic code. * Basics of UVM. * Design questions like counter, FSM, and pipelining. * Verilog questions on execution of the code. * Determine output for a snippet of code in Verilo
Machine Learning Engineer
Chandler, Arizona, United StatesOctober 1, 2021First, I have an interview with the team manager. After I pass the first interview, the technical interview follows. This interview takes 2 hours and the questions are mostly about the basic concepts of machine learning and deep learning. Then, I'm
Software Engineer
Chandler, Arizona, United StatesDecember 1, 2010Flew out to the site and spent a day interviewing. Had four one-hour interviews. The people were very nice. The interviews were difficult, primarily because so much time was spent on them, and it was exhausting. Additionally, there was lunch with t
FPGA Simulation Verification
Chandler, Arizona, United StatesOctober 1, 20211 screening - 5 onsite rounds. Tested on SystemVerilog. * Write FIFO logic code. * Basics of UVM. * Design questions like counter, FSM, and pipelining. * Verilog questions on execution of the code. * Determine output for a snippet of code in Verilo
