Great place to work
Great place to work
No micromanagement faced so far. Great office environment.
Nothing as such, I felt, at the organization.
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Intel Interview Questions
Intel Interview Experiences
Verification Engineer
I had a 5-hour face-to-face interview at Intel's 4B campus for a verification role. I was a fresher then, less confident, and I flunked it. Initially, I had a telephonic interview and was later called to Bangalore for a solid interview. Be strong in
Verification Engineer
The first round was a written test. The difficulty level of the questions was average. The written test was completely technical based. Selected candidates were then taken to the face-to-face round.
Verification Engineer
I was interviewed and demonstrated depth of knowledge in UVM, SV, basic design concepts for FIFOs, and Verilog code for a clock divider. When it came to UVM, I was asked for the difference between a sequence and a sequencer.
Verification Engineer
Bengaluru, Karnataka, IndiaMay 1, 2015I had a 5-hour face-to-face interview at Intel's 4B campus for a verification role. I was a fresher then, less confident, and I flunked it. Initially, I had a telephonic interview and was later called to Bangalore for a solid interview. Be strong in
Verification Engineer
Bengaluru, Karnataka, IndiaMarch 1, 2019The first round was a written test. The difficulty level of the questions was average. The written test was completely technical based. Selected candidates were then taken to the face-to-face round.
Verification Engineer
Bengaluru, Karnataka, IndiaFebruary 1, 2020I was interviewed and demonstrated depth of knowledge in UVM, SV, basic design concepts for FIFOs, and Verilog code for a clock divider. When it came to UVM, I was asked for the difference between a sequence and a sequencer.
