Great Team, Too Much Work
Great Team, Too Much Work
Learning is good, and good understanding with the team.
The salary is not good, and the workload is too much. There is so much more.
Excellent
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Intel Interview Questions
Intel Interview Experiences
Verification Engineer
The interview process was conducted via a telephonic interview. It consisted of a single round that lasted for one hour. Three senior Verification Engineers conducted the interview, and each senior engineer asked questions.
Verification Engineer
Phone interview and then an onsite full-day interview.
Verification Engineer
I was interviewed and demonstrated depth of knowledge in UVM, SV, basic design concepts for FIFOs, and Verilog code for a clock divider. When it came to UVM, I was asked for the difference between a sequence and a sequencer.
Verification Engineer
Pune, Maharashtra, IndiaJuly 1, 2016The interview process was conducted via a telephonic interview. It consisted of a single round that lasted for one hour. Three senior Verification Engineers conducted the interview, and each senior engineer asked questions.
Verification Engineer
United StatesApril 10, 2013Phone interview and then an onsite full-day interview.
Verification Engineer
Bengaluru, Karnataka, IndiaFebruary 1, 2020I was interviewed and demonstrated depth of knowledge in UVM, SV, basic design concepts for FIFOs, and Verilog code for a clock divider. When it came to UVM, I was asked for the difference between a sequence and a sequencer.
