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ASIC Design Engineer Interview Experience - San Jose, California

March 1, 2013
Neutral ExperienceNo Offer

Process

Let me do an introduction, also about my resume.

Questions

Two questions:

  1. 2 2bits comparators to 4 bits comparators, and reduce the delay to 1 units
  2. data buffer like 0100000001, most simple rtl design to get the length (which is 9)

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Interview Statistics

The following metrics were computed from 2 interview experiences for the Marvell Technology ASIC Design Engineer role in San Jose, California.

Success Rate

50%
Pass Rate

Marvell Technology's interview process for their ASIC Design Engineer roles in San Jose, California is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive0%
Neutral100%
Negative0%

Candidates reported having mixed feelings for Marvell Technology's ASIC Design Engineer interview process in San Jose, California.

Marvell Technology Work Experiences