I was offered 2 phone interviews. And then have an onsite interview. They pay for the flight and hotel. Their interviews are quite difficult.
In the 1st phone, they asked to describe MESI's all transitions on phone. And most questions are on CPU design. They asked a lot of implementation details.
They asked a lot of questions on pipeline design.
They were like how to optimize the overall IPC regarding branch? Is it possible to get branch resolved in decode stage?
The following metrics were computed from 36 interview experiences for the Marvell Technology ASIC Design Engineer role in United States.
Marvell Technology's interview process for their ASIC Design Engineer roles in the United States is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Marvell Technology's ASIC Design Engineer interview process in United States.