ASIC Design Verification Engineer Interview Experience - United States
Process
Got the interview opportunity through a career fair. The interview was scheduled in three days. Two phone interview followed by a onsite interview. First phone interview started as technical No HR conversation in the beginning.
Questions
Virtual memory Standard libraries in C How to build a cache How will you move data in cache What is recursion Linked lists, Binary tree, Flat architecture, How a CPU would work
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Interview Statistics
The following metrics were computed from 1 interview experience for the Marvell Technology ASIC Design Verification Engineer role in United States.
Success Rate
Marvell Technology's interview process for their ASIC Design Verification Engineer roles in the United States is extremely selective, failing the vast majority of engineers.
Experience Rating
Candidates reported having mixed feelings for Marvell Technology's ASIC Design Verification Engineer interview process in United States.
Marvell Technology Work Experiences
- 5.0Solid technoligy focused companyASIC Design Verification Engineer • Current EmployeeTel Aviv-YafoMarch 24, 2023Pros: Profesional organization & employees. Very good attitude towards engineers, including work environment and personal time.Cons: Same as other "big" companies, sometimes the action comes from above with nothing you can do about it (except complain and talk)
- 4.0Stable, but slightly bureaucraticASIC Design Verification Engineer • Former EmployeeTel Aviv-YafoJanuary 27, 2023Pros: The company has interesting, large, and challenging projects. It is stable. I suggest a partnership.Cons: Slightly bureaucratic, decision making could take time.
- 5.0ASIC verification engineerASIC Design Verification Engineer • Former EmployeePetah Tikva, IsraelAugust 15, 2014Pros: Interesting work, nice people, good conditionsCons: I didn't find any remarkable cons.
