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Design Verification Engineer Interview Experience - San Jose, California

January 1, 2010
Neutral ExperienceNo Offer

Process

The position was for a mixed signal design verification engineer. It was a pretty tough interview. They asked everything from software to hardware possible in the resume. Methodologies for verification, software concepts related to simulator design. Data structures. Analog concepts from DACs to PLLs and Verilog-A concepts....

Questions

Transfer function of a simple VCO

question on packet transfer inside of test bench from generator to driver... (system verilog concepts)

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Interview Statistics

The following metrics were computed from 2 interview experiences for the Marvell Technology Design Verification Engineer role in San Jose, California.

Success Rate

0%
Pass Rate

Marvell Technology's interview process for their Design Verification Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral50%
Negative50%

Candidates reported having very negative feelings for Marvell Technology's Design Verification Engineer interview process in San Jose, California.

Marvell Technology Work Experiences