The position was for a mixed signal design verification engineer. It was a pretty tough interview. They asked everything from software to hardware possible in the resume. Methodologies for verification, software concepts related to simulator design. Data structures. Analog concepts from DACs to PLLs and Verilog-A concepts....
Transfer function of a simple VCO
question on packet transfer inside of test bench from generator to driver... (system verilog concepts)
The following metrics were computed from 2 interview experiences for the Marvell Technology Design Verification Engineer role in San Jose, California.
Marvell Technology's interview process for their Design Verification Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.
Candidates reported having very negative feelings for Marvell Technology's Design Verification Engineer interview process in San Jose, California.