Design Verification Engineer Interview Experience - Santa Clara, California
Process
Initial phone screen (2) by hiring manager + junior employee (<3 years out of college).
Manager asks conceptual and higher level questions. Junior employee asks coding questions (dictates a piece of code and asks questions on that (SystemVerilog)
Have to fill out online profile and NDA before going onsite.
Onsite interview start with meeting HR person who collects compensation information and asks questions like why you left each of your previous employers, why you are applying now, what other companies you are talking to, what factors you will use to decide the offer etc. Later met with hiring manager (heads design+verif), 1 design engineer and 2 verif engineers (junior+senior).
Hiring manager asks high level questions: e.g where will you place coverage collection for stimulus applied to DUT (monitor Vs driver)
Junior verif person asks more coding questions and behavioural interview (how to deal w/ difficult person, failures in past etc)
Design engineer asks some Verilog question and how to test a particular design.
I give all of them an A for the interview.
Other Sr verif engineer was extremely challenged even to speak couple of sentences in English. He just thrust a piece of paper in front of me typed with a couple of questions. They had non standard terminology and despite repeated requests to explain the terms refused to do so. He kept repeating "just read the question and answer it". After some time I figured out what was the question and gave the answer. He claimed the answer was wrong and asked me to try again. After I came back I googled and found that my answer was correct. He could have moved on to additional questions and had a better/larger sample to make a decision, but stuck with the 2 questions throughout the 45 minute interview. This person should have been trained and lacked basic communication/interview skills in English.
Be prepared for coding questions (some code w/ bug in it etc) regardless of how experienced you are.
Questions
How will you deal with a difficult design engineer?
What will you do if you made a big mistake?
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Interview Statistics
The following metrics were computed from 4 interview experiences for the Marvell Technology Design Verification Engineer role in Santa Clara, California.
Success Rate
Marvell Technology's interview process for their Design Verification Engineer roles in Santa Clara, California is extremely selective, failing the vast majority of engineers.
Experience Rating
Candidates reported having very good feelings for Marvell Technology's Design Verification Engineer interview process in Santa Clara, California.
Marvell Technology Work Experiences
- 4.0ReviewDesign Verification Engineer • Current EmployeeSanta Clara, CaliforniaAugust 17, 2026Pros: It was a good environment.Cons: I can consider joining in some scenarios.
- 4.0Good company to work for, great benefitsDesign Verification Engineer • Former EmployeeSanta Clara, CaliforniaAugust 15, 2010Pros: Knowledgeable people Good communication between manager and myself Good benefits: free food (they don't have that anymore, they still have food for a low price though...), gym, ESPP, stock options upon hire Good salary raiseCons: Sometimes, I had to work long hours.
- 3.0OK CompanyDesign Verification Engineer • Current EmployeeSanta Clara, CaliforniaNovember 22, 2013Pros: Very nice people around, good food, you can learn a lot during the first years. The company is changing, and that is good.Cons: There is not so good of a base salary. We do not have a clear career path. The salary is not growing. Sometimes we need to work very late.
