Great place to work
Great place to work
The team is great and has a very good work environment.
You have to be living in Kanata, Ontario.
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Marvell Technology Interview Experiences
Design Verification Engineer
There were two technical rounds I attended. Both are on SystemVerilog, digital, and UVM. I suggest brush your digital concepts well. Make sure you work on System Verilog constraint thoroughly.
Design Verification Engineer
Phone interview
Design Verification Engineer
There were total 5 ppl included the HR. And it took about 5 more hours. Each interviewer took about an hour to talk with me, and all the questions are technical based. Some of them from my project experience and some of them are design aspect and som
Design Verification Engineer
California City, CaliforniaNovember 1, 2023There were two technical rounds I attended. Both are on SystemVerilog, digital, and UVM. I suggest brush your digital concepts well. Make sure you work on System Verilog constraint thoroughly.
Design Verification Engineer
October 30, 2012Phone interview
Design Verification Engineer
Santa Clara, CaliforniaMarch 1, 2011There were total 5 ppl included the HR. And it took about 5 more hours. Each interviewer took about an hour to talk with me, and all the questions are technical based. Some of them from my project experience and some of them are design aspect and som
