Good company, good potential, underpaid and understaffed
Good company, good potential, underpaid and understaffed
- Good products in the pipeline
- Company has potential
- Good food & benefits
- It looks like management is trying to improve the culture
(At least in my team)
- Over-commitment to customers, and then expecting employees to work more without any additional resources and compensation
- Because everyone is busy doing their stuff, they don't have time to help someone on another team, which leads to a communication gap between the two teams.
- Unable to hire people because of low pay, and a bad reputation.
- After seeing the chaos, two good, knowledgeable people ran away from my team within joining of 6-month.
- No definite plans for onboarding new people. No training for the new hires, or recent grades.
- Bad product documents (TI, NXP, etc doing way better in this department)
Additional Ratings
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Marvell Technology Interview Experiences
ASIC Design Engineer
I have applied this position on line last year. I have received a phone interview last week and there will be a phone interview this week. Asked the basic questions about the ASIC design and questions about the resume. Clock skew and jitter. Blocking
ASIC Design Engineer
I submitted job application 8 months ago online. No HR contacted. Directly contacted by hiring manager and set up one phone call about 45 min, then onsite interview about 6 hours.
Design Verification Engineer
There were two technical rounds I attended. Both are on SystemVerilog, digital, and UVM. I suggest brush your digital concepts well. Make sure you work on System Verilog constraint thoroughly.
ASIC Design Engineer
Santa Clarita, CaliforniaJanuary 1, 2016I have applied this position on line last year. I have received a phone interview last week and there will be a phone interview this week. Asked the basic questions about the ASIC design and questions about the resume. Clock skew and jitter. Blocking
ASIC Design Engineer
Aliso Viejo, CaliforniaMay 24, 2014I submitted job application 8 months ago online. No HR contacted. Directly contacted by hiring manager and set up one phone call about 45 min, then onsite interview about 6 hours.
Design Verification Engineer
California City, CaliforniaNovember 1, 2023There were two technical rounds I attended. Both are on SystemVerilog, digital, and UVM. I suggest brush your digital concepts well. Make sure you work on System Verilog constraint thoroughly.
