Really good work life balance
Really good work life balance
There is enough work to keep you interested.
Sometimes visibility into company future is limited
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Marvell Technology Interview Experiences
Associate Engineer
I got this job 10 years ago. It was around the dot com bubble. Interview was simple. Different people covered different topics from CMOS design, combinational logic, Verilog, board design, instruments, puzzles, etc. But the process still seemed ad-ho
Validation Engineer
Phone interview lasted for 30 mins, asked basically architecture questions. On site interview consists of seven 1:1 interview ranging from programming language like C, PERL and system verilog. Logic questions include timing analysis and logic gates.
ASIC Design Engineer
I received a call for an onsite interview as I was in Santa Clara itself. I gave first onsite with 3 engineers. After 15-20 days I received call for another onsite with 4 engineers. The interviews were pretty basic stuff related to Verilog basics, FS
Associate Engineer
Santa Clara, CaliforniaJanuary 3, 2014I got this job 10 years ago. It was around the dot com bubble. Interview was simple. Different people covered different topics from CMOS design, combinational logic, Verilog, board design, instruments, puzzles, etc. But the process still seemed ad-ho
Validation Engineer
Santa Clara, CaliforniaJune 1, 2010Phone interview lasted for 30 mins, asked basically architecture questions. On site interview consists of seven 1:1 interview ranging from programming language like C, PERL and system verilog. Logic questions include timing analysis and logic gates.
ASIC Design Engineer
Santa Clara, CaliforniaNovember 1, 2014I received a call for an onsite interview as I was in Santa Clara itself. I gave first onsite with 3 engineers. After 15-20 days I received call for another onsite with 4 engineers. The interviews were pretty basic stuff related to Verilog basics, FS
