ASIC Design Verification Engineer Interview Experience - San Jose, California
Process
I applied through a recruiter.
The interviewer asked about my experience and gave some information about the team. They asked questions based on SV Queues and Array sum()s. Overall, the experience was great! They asked a few more technical questions about UVM and also AI usage.
Questions
Write an SV constraint to add K elements J times.
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Interview Statistics
The following metrics were computed from 1 interview experience for the Meta ASIC Design Verification Engineer role in San Jose, California.
Success Rate
Meta's interview process for their ASIC Design Verification Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.
Experience Rating
Candidates reported having very good feelings for Meta's ASIC Design Verification Engineer interview process in San Jose, California.
Meta Work Experiences
- 4.0Great perks, WLB can be betterASIC Design Verification Engineer • Current EmployeeSan Jose, California, United StatesAugust 7, 2025Pros: Great perks and projects. Great team.Cons: Work-life balance can get super worse.
- 5.0Excellent Compensation, Happy EmployeeSoftware Engineer • Current EmployeeSan Jose, California, United StatesMarch 10, 2021Pros: Best make tons of money.Cons: Nothing. I'm happy about everything. Great company.
- 3.0Good Company, Wasted PotentialSoftware Engineer • Former EmployeeSan Jose, California, United StatesJuly 10, 2025Pros: Good company, Zuck is doing a great job!Cons: Too much focus on useless products
Meta Interview Questions
