The work-life balance is great.
Compensation is low post initial stock grant (cliff), and retention is poor.
I submitted my application online around fall of 2015 and was contacted a few weeks later for an on-campus interview at my university. At the on-campus interview, I was asked behavioral questions and then tested on: * NAND gate truth table * K-map *
I did pretty well on the phone interview but was declined 3 days later. The questions were mostly about what I had on my resume. They also expected me to know verification and UVM with Verilog, even though my university didn't offer those courses.
There were 2 main rounds. The first round was mostly behavioral, with some RTL and OOP coding questions. The second round had 4 different sessions with 3 engineers and 1 manager. These were all about design and verification using System Verilog.
I submitted my application online around fall of 2015 and was contacted a few weeks later for an on-campus interview at my university. At the on-campus interview, I was asked behavioral questions and then tested on: * NAND gate truth table * K-map *
I did pretty well on the phone interview but was declined 3 days later. The questions were mostly about what I had on my resume. They also expected me to know verification and UVM with Verilog, even though my university didn't offer those courses.
There were 2 main rounds. The first round was mostly behavioral, with some RTL and OOP coding questions. The second round had 4 different sessions with 3 engineers and 1 manager. These were all about design and verification using System Verilog.