Two 45-minute interviews back-to-back without a break.
One technical session and one coding session (Verilog or SystemVerilog).
I got rejected after about two days, but I was still able to interview with other teams.
The first interview asked basic technical questions about logic design, STA, and FSM, etc. The second one was RTL coding for a synchronous FIFO with depth=5.
The following metrics were computed from 1 interview experience for the Nvidia ASIC Design Engineer Intern role in San Diego, California.
Nvidia's interview process for their ASIC Design Engineer Intern roles in San Diego, California is extremely selective, failing the vast majority of engineers.
Candidates reported having mixed feelings for Nvidia's ASIC Design Engineer Intern interview process in San Diego, California.