Phone interview
Design gates using CMOS transistors.
Build gates using 2-to-1 muxes.
Write a Verilog module that takes a clock signal and outputs another clock signal that is 3 times lower in frequency.
The number of states required for a sequence recognizer.
Phone interview
The following metrics were computed from 1 interview experience for the Nvidia ASIC Intern role in Canada.
Nvidia's interview process for their ASIC Intern roles in Canada is extremely selective, failing the vast majority of engineers.
Candidates reported having mixed feelings for Nvidia's ASIC Intern interview process in Canada.