Attended the first round.
Going to attend the second and third rounds.
ASIC intern at Santa Clara.
Design XOR2 gate using two 2-input MUXes, inputs A and B, power, and ground.
Setup and hold time definitions: there is a branch with one path being setup critical, and another with a hold violation. Given a buffer, where will you place it if both paths should not have violations?
Where are Gray counters used?
Design XOR2 gate using only NAND2 gates.
Four men, one bridge, can cross two at a time, only one flashlight. Each one takes 1, 2, 5, and 10 minutes to cross one way. Minimum time for all four to cross the bridge.
The following metrics were computed from 4 interview experiences for the Nvidia ASIC Intern role in United States.
Nvidia's interview process for their ASIC Intern roles in the United States is very selective, failing most engineers who go through it.
Candidates reported having very good feelings for Nvidia's ASIC Intern interview process in United States.