1. Interview on Phone

Round 1

• Two to Three Qs on Projects done
• Designing Q: Consider inputs coming at every clock. I want the output at time = t to give the sum of all numbers coming before that time. (Adder is a normal adder with latency 1)
• Designing Q: Consider the same output needed, but the adder has a latency of 2. Input is taken at every clock, and the output is given at every clock. Input at t=0 is received at the output at t=2; input at t=1 is received at the output at t=3...

Round 2

• RTL coding
• C, C++ pointer questions
• How to do VHDL coding
• FSM Sequence detector
• How will you verify the FSM code
• Design Using Shift Registers
• How will you code this

Round 3

• Add 7 bits using 4 Full Adders
• Two pipelines running in parallel. 128-bit register file. 4 read ports and 2 write ports. Convert it into 4 reg files with one read and one write port for all. Find advantages and disadvantages.
• Design a divide-by-3 FSM checker