I applied online.
Recruiter call was short: work history and biggest projects. Then a technical screen that ran almost 2 hours—mix of everything, some Linux scripting, a bit of SV, a small spec where I had to talk through what I'd verify and how. Nothing individually hard, but it was non-stop question after question, and I didn't get time for my own at the end. I noticed they take a normal question and remove the keyword you'd use for it, like randc without the builtin.
Onsite was 5 rounds back-to-back, 1 hour each, all future teammates. They don't split by topic, so every round was a bit of digital design, a bit of SV, some comp arch. FSM came up more than once, same with constraints written the hard way. The one I remember most was a UVM round where they gave me a working TB and said a new interface is being added to the DUT, how do you update it. They interrupted a lot on that to counter into connections. Some MESI and CDC questions too. No behavioral rounds really, just a few "Why NVIDIA?" type questions here and there.
For prep:
Did a mock with an NVIDIA DV coach on Prepfully; main feedback was I kept using my company's names for UVM components instead of standard ones, which made my experience sound narrower than it was—would not have caught that myself. Also fumbled a basic dynamic array declaration in the mock, and he said that kind of slip hurts more than struggling on a hard problem, so don't skip the basics, I'd say.
The following metrics were computed from 2 interview experiences for the Nvidia Design Verification Engineer role in Santa Clara, California.
Nvidia's interview process for their Design Verification Engineer roles in Santa Clara, California is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Nvidia's Design Verification Engineer interview process in Santa Clara, California.