Ask project-relevant questions, then go through some textbook questions relative to STA (Static Timing Analysis) and normal clock frequency analysis.
Cover logic gates and some Verilog programming.
In the end, answer several of my questions.
Generate a clock divider using an OR gate.
The following metrics were computed from 1 interview experience for the Nvidia Digital Verification Engineer role in San Jose, California.
Nvidia's interview process for their Digital Verification Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Nvidia's Digital Verification Engineer interview process in San Jose, California.