The interview process involved two technical phone screens and six rounds of onsite interviews, which were conducted entirely via video call and were almost exclusively technical.

Interestingly, there were very few behavioral questions. Instead, the focus was on technical aspects, including details of past projects and the requirements for the future role.

SystemVerilog skills (especially assertions).

General (high-level) questions of how verification methodologies work (e.g., constrained random, UVM, formal).

Design a finite state machine for a given task.