I had two phone interviews.
The first round had:
The next round had:
Calculate FIFO depth for the following data rate:
Writing Data = 80 DATA/100 Clock (Randomization of 20 Data's) Outgoing Data = 8 DATA/10 Clock. Burst size = 160
UVM Hierarchy related questions:
Can a Monitor talk to the design? If yes, then how?
How can a sequence item reach the DUT?
What is a synchronizer? What does it do? Why is it used?
Effective way of array sorting?
The following metrics were computed from 1 interview experience for the Nvidia Verification Internship role in Santa Clara, California.
Nvidia's interview process for their Verification Internship roles in Santa Clara, California is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Nvidia's Verification Internship interview process in Santa Clara, California.