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Verification Internship Interview Experience - Santa Clara, California

February 1, 2020
Positive ExperienceNo Offer

Process

I had two phone interviews.

The first round had:

  • One analytical ability question.
  • One calculating the FIFO depth question.
  • One FSM Verilog question.

The next round had:

  • One question on sorting algorithms.
  • One on synchronizers.
  • UVM hierarchy type questions.

Questions

Calculate FIFO depth for the following data rate:

Writing Data = 80 DATA/100 Clock (Randomization of 20 Data's) Outgoing Data = 8 DATA/10 Clock. Burst size = 160

UVM Hierarchy related questions:

Can a Monitor talk to the design? If yes, then how?

How can a sequence item reach the DUT?

What is a synchronizer? What does it do? Why is it used?

Effective way of array sorting?

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Interview Statistics

The following metrics were computed from 1 interview experience for the Nvidia Verification Internship role in Santa Clara, California.

Success Rate

0%
Pass Rate

Nvidia's interview process for their Verification Internship roles in Santa Clara, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Nvidia's Verification Internship interview process in Santa Clara, California.

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