Good place to learn, bad place to earn
Good place to learn, bad place to earn
There are lots of things to learn.
There are lots of projects to do.
There are opportunities in many fields.
One can do design work, verification, or FPGA.
All are there.
Too much politics. Too much emphasis on email and bug reports. The "Rally" tool sucks the life out of you. Middle management is clueless. Not good pay.
Fire dumb managers and employees. Reward good ones.
Was this helpful?
Nvidia Interview Questions
Nvidia Interview Experiences
Senior ASIC Design Engineer
The interview process consisted of two tech screens, followed by a panel. Interview questions were standard design problems, targeting both Verilog coding ability and problem-solving skills. Interviewers looked more at thought process than specific s
Senior ASIC Design Engineer
I applied online. The process took 4 days. It was a screening round. The whole interview was based on a single Digital Design question. He was not helping me much; when I was not able to solve it, I told him about my thinking and then he helped, but
Senior ASIC Design Engineer
The interview was managed very professionally. The questions asked were purely technical and related to the basic fundamentals of electronic design/chip design.
Senior ASIC Design Engineer
Santa Clara, California, United StatesNovember 4, 2025The interview process consisted of two tech screens, followed by a panel. Interview questions were standard design problems, targeting both Verilog coding ability and problem-solving skills. Interviewers looked more at thought process than specific s
Senior ASIC Design Engineer
San Jose, California, United StatesMarch 21, 2026I applied online. The process took 4 days. It was a screening round. The whole interview was based on a single Digital Design question. He was not helping me much; when I was not able to solve it, I told him about my thinking and then he helped, but
Senior ASIC Design Engineer
Bengaluru, Karnataka, IndiaMay 1, 2011The interview was managed very professionally. The questions asked were purely technical and related to the basic fundamentals of electronic design/chip design.
