I had 3 rounds of medium level that were all technical, covering System Verilog, UVM, logics, ABP, AHB, UART, and SPI.
I had 3 rounds of medium level that were all technical, covering System Verilog, UVM, logics, ABP, AHB, UART, SPI, and a question based on work history.
System verilog formats based on previous experience questons
The following metrics were computed from 4 interview experiences for the NXP Semiconductors Design Verification Engineer role in India.
NXP Semiconductors's interview process for their Design Verification Engineer roles in India is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for NXP Semiconductors's Design Verification Engineer interview process in India.