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ASIC Design Verification Engineer Interview Experience - San Diego, California

January 1, 2021
Positive ExperienceNo Offer

Process

It was a 5-stage virtual interview process with 5 different people from the team. It was my first virtual interview, and it was really a different experience compared to a phone interview.

Questions

All the interviewers were Indians and were really nice. I had a good conversation during each interview, which lasted about an hour.

Everyone had a set of questions prepared and asked me to solve them.

  1. Full SV:

    • Fork join_none, virtual functions, $cast, static variable, cache size (direct mapping), MESI FSM, constraints, parity check (post randomize).
  2. STA:

    • Hold violations, max frequency, FIFO depth, metastability.
  3. DUT:

    • Multi-master multi-slave bridge verification (draw the environment and test cases), AXI signals.
  4. UVM:

    • Phases, AXI vs. APB, AXI Lite vs. AXI 3.0, driver code, coverage class, and cross-coverage.
  5. HR:

    • Teamwork, resources used in a project, setbacks faced. Explained most employee benefits, applying for H1B and green card, etc.

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Interview Statistics

The following metrics were computed from 1 interview experience for the Qualcomm ASIC Design Verification Engineer role in San Diego, California.

Success Rate

0%
Pass Rate

Qualcomm's interview process for their ASIC Design Verification Engineer roles in San Diego, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Qualcomm's ASIC Design Verification Engineer interview process in San Diego, California.

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