ASIC Design Verification Engineer Interview Experience
Process
They asked me a riddle.
I was tested on various digital design concepts. I was also tested on:
- C++
- Writing SystemVerilog concepts based on simulation output
- General verification concepts (no UVM yet)
I was also asked about my long-term goals and to what extent I understand the company's work.
Questions
I can't say exactly, but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
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Interview Statistics
The following metrics were computed from 2 interview experiences for the Qualcomm ASIC Design Verification Engineer role in United States.
Success Rate
Qualcomm's interview process for their ASIC Design Verification Engineer roles in the United States is extremely selective, failing the vast majority of engineers.
Experience Rating
Candidates reported having very good feelings for Qualcomm's ASIC Design Verification Engineer interview process in United States.
Qualcomm Work Experiences
- 5.0Supportive and EncouragingASIC Design Verification Engineer • Former EmployeeChennai, Tamil Nadu, IndiaNovember 5, 2019Pros: Worked on cutting-edge technologies, developed standard and efficient programming skills, and improved time management. Enjoyed team outings.Cons: The free lunch provided was bad.
- 4.0Good place to workASIC Design Verification Engineer • Former EmployeeBengaluru, Karnataka, IndiaOctober 20, 2021Pros: Faster project timelines. Good food, gym, and other amenities. Periodic fun team activities.Cons: Hikes are a little low sometimes. Tough to switch within the company.
- 4.0Great Management, Better PayASIC Design Verification Engineer • Current EmployeeSanta Clara, California, United StatesApril 5, 2021Pros: Good company with nice management.Cons: Good company, but can pay more compensation.
Qualcomm Interview Questions
