I applied through a recruiter. The process took 2 weeks.

The interview process for an ASIC Design Verification (DV) Engineer typically includes resume screening, one or more technical phone or online interviews focusing on digital fundamentals, SystemVerilog, UVM, and debugging skills, followed by multiple in-depth technical and behavioral interview rounds assessing verification methodology, problem-solving ability, and teamwork.

They mainly asked me to explain how to build and debug a UVM-based verification environment, including the roles of sequences, drivers, monitors, scoreboards, and how I handled a real bug or coverage issue during a project.