The process started when a recruiter contacted me via LinkedIn. An exchange of resumes led to a phone interview with the hiring manager and a technical team member. The phone conversation went well; it flowed easily, and we discussed both technical and leadership questions. What was planned as a 15-minute conversation pleasantly extended to an hour. I was then invited for an on-site interview. Travel planning went smoothly, all via email. My hotel was located just down the road from the offices, so I had no problem arriving early for the interview.

The start time had been delayed multiple times. Consequently, each meeting was very short, which clipped discussions and made design-on-the-fly tasks very difficult. Lunch with the hiring manager and another team member was very nice, pleasant, and relaxed, even though more technical questions arose during the conversation.

I submitted my trip expenses and was informed in a confirmation email that reimbursement could take up to 90 days. I am still waiting, and it has been 80 days.

Given a white-board diagram of a block with a FIFO and a verbal description of the block's inputs and outputs, write on the white board the Verilog or SystemVerilog for the design. I had 15 minutes. Why would you want someone who goes straight to code with no planning? That usually results in spaghetti code that has to be rewritten.

White-board diagram of a block with one input pin (+ clock) and one output pin. The input is a serial stream of data. The output is 1 whenever the pattern "0110" has been seen on the serial data. Everything is synchronous to the clock input. Write the Verilog.

Given the shortened time constraint for the interview, diagram the design solution. In addition to what you come up with, write a bubble diagram for an FSM solution.