I received a phone call first. The basic concentration was on testbench experience, work experience, how you develop a testbench, UVM/OVM basics, test planning basics, PCI Express knowledge, and work experience.

I did very well, but they took more than 30 days to get back. I was invited for an onsite interview.

It lasted for six rounds.

• Round 1: Clock domain crossing (CDC) issues, how to solve them, what to do if it's a bus, design a FSM, behavioral codes for divide by 2 and 3 using shift registers, metastability, how to solve it, and how to model it in the environment.
• Round 2: CDC, PCS layer, PCI Express school project, PHY layer questions, how to implement in behavioral modeling, testbench architecting questions, CDC FIFO questions, block-level model. Why 8b/10b encoding in PCIe, how signaling is done, LTSSM questions.
• Round 3: SV basics, Verilog basics, delays, waveforms, timing, fixes, and other questions that didn't make much sense. Their answers were very theoretical, not practical applications.
• Round 4: Same questions from previous rounds. More concentration on how a PCIe device works, various layers, test planning, testbench development, execution-related questions, and more technical questions.
• Round 5: Lunch. Behavioral questions, my experience in various scenarios.
• Round 6: Same questions from previous rounds. My environment questions, UVM, SV questions, Perl code, PLL questions, PHY-related questions.

It was a good interview process. They grilled every aspect, but the decision-making was insane. I did extremely well, but they still didn't get back, and I had another offer. The team members were very nice.