My resume was picked from their online database, and I was called for an onsite interview directly, without a phone interview.

The position was for a SOC/ASIC designer. I was interviewed by five people, each for an hour, mostly on digital design, timing analysis, synthesis, course projects, and design problems.

One of the interviewers had a specific list of questions and a time frame for each. He apparently rushed me through it, which put pressure on an already tensed candidate!

Although I thought I did fairly well, it didn't work out.

My advice for people in this field: Know these things well: Verilog, state diagrams, timing analysis, flip-flop/latch designs, synthesis, and industry-standard CAD tools.

Calculate and meet setup/hold times with positive/negative clock skew and buffers in a case where the skew can be both positive and negative, and you don't know which.