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Validation Engineer Interview Experience - San Jose, California

February 1, 2016
Positive ExperienceGot Offer

Process

Had two telephonic rounds and an onsite interview of four rounds.

Each telephonic round was for about 45 minutes. Several questions covered SystemVerilog and UVM, and Perl.

Key topics included:

  • The difference between a queue and a mailbox.
  • Explaining fork-join.
  • How to declare a memory in SystemVerilog.

The onsite interview focused on UVM and SV verification questions, and scripting.

Scripting topics included how to determine the size of an array in Perl.

There were also questions on the projects mentioned in the resume.

Questions

  1. Explain the test bench architecture that you worked on.

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Interview Statistics

The following metrics were computed from 1 interview experience for the Qualcomm Validation Engineer role in San Jose, California.

Success Rate

100%
Pass Rate

Qualcomm's interview process for their Validation Engineer roles in San Jose, California is incredibly easy as the vast majority of engineers get an offer after going through it.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Qualcomm's Validation Engineer interview process in San Jose, California.

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