Fast Growth, Less Design
Fast Growth, Less Design
A lot of young talent. The site is growing fast.
Lots of projects in parallel. Not making a lot of actual HDL design.
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Qualcomm Interview Experiences
ASIC Design Engineer
The interviewer was friendly. They covered topics on: * Computer architecture * Static Timing Analysis * System Verilog * UVM They went in-depth on AHB, synchronizers, and CDC. It was a good overall experience.
ASIC Design Engineer
The interview is scheduled from 9:30 am to 4:50 pm. There are six interviewers. The first interviewer will ask for your information. The other five interviewers will ask technical questions. They may ask you questions even during your lunch break
ASIC Design Engineer
Phone Interview I received a call directly for a phone interview on the third day, without any prior scheduling. I was very surprised by the timing, as it was around 4:30 PM. The interview lasted for over 30 minutes. I am not sure where it went wro
ASIC Design Engineer
United StatesMarch 11, 2021The interviewer was friendly. They covered topics on: * Computer architecture * Static Timing Analysis * System Verilog * UVM They went in-depth on AHB, synchronizers, and CDC. It was a good overall experience.
ASIC Design Engineer
San Diego, California, United StatesApril 1, 2012The interview is scheduled from 9:30 am to 4:50 pm. There are six interviewers. The first interviewer will ask for your information. The other five interviewers will ask technical questions. They may ask you questions even during your lunch break
ASIC Design Engineer
San Diego, California, United StatesJanuary 1, 2019Phone Interview I received a call directly for a phone interview on the third day, without any prior scheduling. I was very surprised by the timing, as it was around 4:30 PM. The interview lasted for over 30 minutes. I am not sure where it went wro
