The company came through my college placement team for an intern. I took an online test comprising of IQ and technical questions. There were two interviews, both 1:1. The first one consisted of technical questions, and the second was an HR intervi
It was a good experience overall. They asked about various concepts in UVM and SystemVerilog, mainly concentrating on UVM. Topics covered included interfaces, modports, driver-sequencer communication, and more. I was also asked about design concepts
Screen Test • 3 Technical Rounds • OS, DP, LinkedList, Bit Manipulation, and string coding questions • Semaphores, mutexes, OSI layers, etc. Applied via LinkedIn. Went through past interview questions. Bit manipulation and memory management are imp
The company came through my college placement team for an intern. I took an online test comprising of IQ and technical questions. There were two interviews, both 1:1. The first one consisted of technical questions, and the second was an HR intervi
It was a good experience overall. They asked about various concepts in UVM and SystemVerilog, mainly concentrating on UVM. Topics covered included interfaces, modports, driver-sequencer communication, and more. I was also asked about design concepts
Screen Test • 3 Technical Rounds • OS, DP, LinkedList, Bit Manipulation, and string coding questions • Semaphores, mutexes, OSI layers, etc. Applied via LinkedIn. Went through past interview questions. Bit manipulation and memory management are imp