Lots of learning opportunities here.
Sometimes work gets tricky here.
The telephonic and face-to-face rounds involved technical questions only.
Screen Test • 3 Technical Rounds • OS, DP, LinkedList, Bit Manipulation, and string coding questions • Semaphores, mutexes, OSI layers, etc. Applied via LinkedIn. Went through past interview questions. Bit manipulation and memory management are imp
It was a good experience overall. They asked about various concepts in UVM and SystemVerilog, mainly concentrating on UVM. Topics covered included interfaces, modports, driver-sequencer communication, and more. I was also asked about design concepts
The telephonic and face-to-face rounds involved technical questions only.
Screen Test • 3 Technical Rounds • OS, DP, LinkedList, Bit Manipulation, and string coding questions • Semaphores, mutexes, OSI layers, etc. Applied via LinkedIn. Went through past interview questions. Bit manipulation and memory management are imp
It was a good experience overall. They asked about various concepts in UVM and SystemVerilog, mainly concentrating on UVM. Topics covered included interfaces, modports, driver-sequencer communication, and more. I was also asked about design concepts