Sr. SOC Design Engineer - STA, Hardware Compute Group

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer-STA to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.

Roles & Responsibilities:

• Definition and development of signoff methodology and corresponding implementation solution
• Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs
• Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC
• Streamlining the timing signoff criterions, timing analysis methodologies and flows
• Analyze and incorporate advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow
• Work with Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal, IP owners, Synthesis, Place & Route and other local/remote teams to address design challenges in the context of timing sign-off
• Concepts of CRPR, clock paths analysis and tweaks to meet timing
• Multi Corner and Multimode analysis
• Close timing at Signoff corners covering the entire modes, delay corners for cells and interconnects

This role offers an opportunity to work on cutting-edge technology in the field of ML accelerators and contribute to the development of innovative products like Echo devices. You'll be part of a team that has a track record of revolutionizing user experiences and will have the chance to make a significant impact on future generations of Amazon's hardware products.