Cellular SOC Design Verification Engineer

As a Cellular SOC Design Verification Engineer at Apple, you'll be part of the innovative Silicon Engineering Group, working on sophisticated SOCs. You'll lead and contribute to verifying complex SOCs, integrating IP-level DV environments, creating reusable UVM test benches, implementing effective test cases, and deploying new tools and methodologies. You'll collaborate with various product development groups to push the boundaries of cellular systems and improve customer experiences worldwide.

Key responsibilities include:

• Understanding high-efficiency SOC architecture and standard peripherals
• Building coverage-driven verification plans
• Creating IP level module and sub-system verification plans and test benches
• Architecting UVM-based reusable test benches and integrating them at the SOC level
• Collaborating with DV methodology architects to improve verification flow

This role requires someone comfortable with all areas of SoC design verification engineering, thriving in a dynamic multi-functional organization, and able to adapt to evolving requirements. You'll have the opportunity to learn about large-scale SOC architecture, high-speed layered protocols, low-power architecture, and cellular protocols.

Qualifications:

• BS and a minimum of 2 years of relevant industry experience
• Dedicated hands-on ASIC DV experience
• Advanced knowledge of HVL methodology (UVM/OVM)
• Experience with full ASIC cycle from concept to tape-out and bring-up
• Hands-on verification experience with PCIe, Bus Fabric, NOC, AHB, AXI
• In-depth knowledge of low-power design and HW/FW interaction verification
• Excellent communication and problem-solving skills

Apple offers a comprehensive benefits package, including medical and dental coverage, retirement benefits, stock options, and educational reimbursement opportunities. The base pay range for this role is between $143,100 and $264,200, depending on skills, qualifications, experience, and location.