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Emulation Verification Engineer

Apple is a technology company that designs, develops, and sells consumer electronics, software, and services.
Mid-Level Software Engineer
In-Person
5,000+ Employees
3+ years of experience
Hardware

Description For Emulation Verification Engineer

Imagine what you'll do at Apple! New insights have a way of becoming extraordinary products, services, and customer experiences very quickly. As a member of the Emulation verification team, you will play a key role in using Emulation for verification of large SoCs. The position involves collaborating closely with Architecture, Design, DV, Silicon Validation, Power and SW teams to bring up large SoCs on emulation platform.

You will be responsible for porting design onto the Palladium platform and completing detailed Emulation testplans. The role requires developing and applying synthesizable monitors/checkers, creating stimulus on emulation platform, and performing low power testing. You'll be working with Verilog/System Verilog/UVM to develop code for Design and verification activities.

The ideal candidate should have strong experience with Standard Emulator (Palladium, Veloce, Zebu) or FPGA (Xilinx, Altera) flow, proven design verification skills, and excellent analytical and debug capabilities. Knowledge of UVM Acceleration is a plus. This role offers an opportunity to work on cutting-edge hardware verification projects at one of the world's most innovative technology companies.

At Apple, we're passionate about changing the world and have a critical impact on getting high quality functional products to millions of customers quickly. Join our design verification team and be at the center of chip design efforts, collaborating with Architecture, Design and SW teams in this highly transparent role.

Last updated a day ago

Responsibilities For Emulation Verification Engineer

  • Collaborate with Architecture, Design, DV, Silicon Validation, Power and SW teams
  • Porting design onto the Palladium platform
  • Completing detailed Emulation testplans
  • Develop/apply synthesizable monitors/checkers, stimulus on emulation platform
  • Perform low power testing on emulation platform
  • Develop code for Design and verification using Verilog/System Verilog/UVM
  • Develop random stimulus infrastructure

Requirements For Emulation Verification Engineer

  • BS + 3 years relevant industry experience
  • Understanding of the tool flow from RTL to Emulation
  • Good understanding of Standard Emulator or FPGA flow
  • Experience in writing Synthesize-able SystemVerilog/Verilog code
  • Experience with System Verilog verification environments
  • Experience with writing and debugging test FW
  • Experience on Scripting (Perl/Python/TCL)
  • Excellent analytical and debug skills

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