PLL/Clocking Design Engineer
Description For PLL/Clocking Design Engineer
At Apple, we're seeking a PLL/Clocking Design Engineer to join our Analog-Mixed/Signal group. In this role, you'll develop cutting-edge frequency synthesizers for various applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple's leadership in innovation and market presence.
Key responsibilities include:
- Leveraging expertise in PLL/FLL and frequency synthesis architecture and circuit design
- Developing both digital and analog approaches, DCO/VCO design (RO and LC), Fractional-N, SSC, Spur and Jitter cancellation techniques
- Applying knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques
- Utilizing deep understanding of clocking fundamentals, phase noise, jitter analysis, budgeting, and feedback loop dynamics
- Developing System Verilog models and performing behavioral simulations
- Collaborating with a team of exceptional individuals passionate about continual learning and making a substantial impact
We offer a dynamic environment that thrives on challenges, encouraging ownership of your career and supported by colleagues committed to making a difference. If you excel in collaborative problem-solving and seek to make a societal impact through your work, this role at Apple could be the perfect fit for you.
Join us in pushing the boundaries of what our technology can achieve and setting new standards in the tech industry.
Responsibilities For PLL/Clocking Design Engineer
- Develop cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies
- Contribute to maintaining Apple's leadership in innovation and market presence
- Apply expertise in digital and analog approaches, DCO/VCO design, Fractional-N, SSC, Spur and Jitter cancellation techniques
- Perform behavioral simulations to explore new architectural performance and impact on loop dynamics
- Collaborate with team members to solve complex problems
- Continuously learn and adapt to new technologies and challenges
Requirements For PLL/Clocking Design Engineer
- BSEE required or years of relevant experience. MSEE preferred
- Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design
- Good knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques
- Deep understanding of clocking fundamentals, phase noise, jitter analysis, budgeting, and feedback loop dynamics
- Skilled in developing System Verilog models and performing behavioral simulations
- Ability to design/debug RTL is a plus
- Exceptional focus on understanding problems and their systemic impacts
- History of innovation and self-directed learning
- Outstanding teamwork capabilities
- Strong productivity and scripting skills
Benefits For PLL/Clocking Design Engineer
- Comprehensive medical and dental coverage
- Retirement benefits
- Discounted products and free services
- Reimbursement for certain educational expenses
- Opportunity to become an Apple shareholder through discretionary employee stock programs
- Employee Stock Purchase Plan
- Potential eligibility for discretionary bonuses or commission payments
- Potential eligibility for relocation assistance
