Digital Verification Engineer
Description For Digital Verification Engineer
Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a Senior Digital Verification Engineer to join their team in San Jose, CA. This is a highly visible role focused on ASIC development for data center connectivity applications.
The ideal candidate will bring 6+ years of experience in digital design verification, along with an MS or PhD in Electrical or Computer Engineering. You'll be working with cutting-edge technology, applying your expertise in SV UVM, processor verification, and various interfaces including SPI, I2C, and AMBA.
This role offers an exciting opportunity to work on complex verification challenges, including analog mixed-signal building blocks, DFT design verification, and development of comprehensive verification plans. You'll be using industry-standard EDA tools from Synopsys/Cadence and applying your knowledge of scripting languages like Python and PERL.
The position comes with a competitive compensation package ranging from $120,000 to $192,000 annually, plus discretionary bonuses and equity awards. Broadcom offers comprehensive benefits including medical, dental, and vision insurance, 401(k) with company matching, ESPP, and various leave benefits.
As part of Broadcom's innovative team, you'll collaborate with talented professionals in a dynamic environment that values technical excellence and creative problem-solving. This role is perfect for a self-starter who enjoys working in a team setting and can communicate effectively across technical and management levels.
The company maintains a strong commitment to diversity and inclusion, providing equal opportunities for all qualified candidates. Join Broadcom and be part of a team that's shaping the future of technology in data center connectivity and beyond.
Responsibilities For Digital Verification Engineer
- Working on ASIC for data center connectivity applications
- Developing metric driven verification plans
- Verification of DFT design, architecture, and microarchitecture
- Generating randomized vectors for analog and digital behavioral model verification
- Performing GLS with & without parasitic annotated simulations
Requirements For Digital Verification Engineer
- MS or PhD in Electrical Engineering or Computer Engineering with 6+ years of experience in digital design verification
- Hands on experience in SV UVM, SV RNM and verification coverage matrix
- Prior experience in processor verification
- Familiarity with SPI, I2C and AMBA interfaces
- Experience with writing regression tests, developing checker, writing assertions
- Prior experience in setting up and maintaining regressions using Verisium Manager
- Familiarity with analog mixed-signal building blocks
- Hands-on knowledge of standard industry EDA tools - Synopsys/Cadence
- Prior experience in generating UVM RAL model
- Proficient with scripting languages like PERL, Python etc.
- Strong written and verbal communication skills
- Self-starter and team player
Benefits For Digital Verification Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Annual discretionary bonus
- Equity awards
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