Digital Verification Engineer
Description For Digital Verification Engineer
Broadcom is seeking an experienced Digital Verification Engineer to join their team in a senior-level position focused on ASIC development for data center connectivity applications. This is a highly visible role within the organization that combines hardware verification expertise with software development skills.
The position requires a strong educational background with either an MS or PhD in Electrical Engineering or Computer Engineering, complemented by at least 6 years of hands-on experience in digital design verification. The ideal candidate will bring extensive knowledge of industry-standard verification methodologies and tools, including SV UVM, SV RNM, and verification coverage matrix development.
Key technical requirements include proficiency with processor verification, familiarity with various interfaces (SPI, I2C, AMBA), and experience with analog mixed-signal components such as ADCs, DACs, PLLs, and SerDes. The role involves working with industry-standard EDA tools from Synopsys and Cadence, and requires expertise in regression testing, assertion writing, and metric-driven verification planning.
Broadcom offers a competitive compensation package with a base salary range of $120,000 to $192,000, plus additional benefits including medical, dental, and vision insurance, 401(k) matching, stock purchase programs, and various leave benefits. The company culture promotes innovation, collaboration, and professional growth, making it an ideal environment for ambitious verification engineers looking to work on cutting-edge semiconductor technology.
The position is based in San Jose, California, at the heart of Silicon Valley, offering opportunities to work with leading-edge technology and collaborate with top talent in the semiconductor industry. This role is perfect for a self-motivated professional who combines technical expertise with strong communication skills and can effectively interact with various stakeholders across technical and management levels.
Responsibilities For Digital Verification Engineer
- Working on ASIC for data center connectivity applications
- Verification of DFT design, architecture, and microarchitecture
- Generating randomized vectors for analog and digital behavioral model verification
- Performing GLS with & without parasitic annotated simulations
Requirements For Digital Verification Engineer
- MS or PhD in Electrical Engineering or Computer Engineering with 6+ years of experience in digital design verification
- Hands on experience in SV UVM, SV RNM and verification coverage matrix
- Prior experience in processor verification
- Familiarity with SPI, I2C and AMBA interfaces
- Familiarity with writing regression tests, developing checker, writing assertions and developing metric driven verification plan
- Prior experience in setting up and maintaining regressions using Verisium Manager
- Familiarity with analog mixed-signal building blocks
- Hands-on knowledge of standard industry EDA tools - Synopsys/Cadence
- Prior experience in generating UVM RAL model
- Proficient with scripting languages like PERL, Python etc.
- Strong written and verbal communication skills
- Self-starter and team player
Benefits For Digital Verification Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Annual discretionary bonus
- Equity awards
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