High Speed SerDes RTL Design Engineer
Description For High Speed SerDes RTL Design Engineer
Broadcom is seeking an experienced High Speed SerDes RTL Design Engineer to lead the development of next-generation AI connectivity solutions. This role combines deep technical expertise with leadership responsibilities, focusing on designing and developing highly integrated SerDes solutions.
The position requires a master's or doctoral degree in Electrical or Computer Engineering, backed by at least 13 years of experience in front-end digital design for high-speed data center networking applications. The ideal candidate will have extensive experience with TSMC 7nm-2nm technology and a comprehensive understanding of high-speed optical/electrical interconnect architectures.
As a Lead RTL Designer, you'll be responsible for driving SOC level front-end design specifications, managing design flows, and ensuring optimal performance in areas such as timing signoff, verification, and IP integration. The role demands strong analytical thinking, problem-solving skills, and the ability to work effectively across internal and customer teams.
Broadcom offers a competitive compensation package, including a base salary range of $163,000 - $262,000, along with comprehensive benefits such as medical, dental, and vision insurance, 401(k) matching, equity awards, and an Employee Stock Purchase Program. The company culture promotes innovation, technical excellence, and collaborative problem-solving.
This position represents an excellent opportunity for a seasoned professional to work at the forefront of AI connectivity technology while contributing to cutting-edge semiconductor solutions. The role combines technical leadership with hands-on design work, making it ideal for someone who enjoys both technical challenges and team leadership.
Responsibilities For High Speed SerDes RTL Design Engineer
- Leading the design and development of highly integrated SerDes solutions
- Providing guidelines for GLS, DFT & Verification
- Evaluating timing signoff, verification and IP Integration
- Driving SOC level front end design specifications
- Assessing design bugs and recommending fixes
- Working effectively across internal and end customers teams
Requirements For High Speed SerDes RTL Design Engineer
- MS or PhD in Electrical Engineering or Computer Engineering
- 13+ years of experience in front end digital design for serial high-speed data center networking applications
- Experience as a Lead digital designer for chip and platform for high bandwidth/high speed SerDes applications
- Experience in integrating front end design with DV for test methodologies and verification
- Experience in design management and development methodologies
- Deep understanding of high-speed optical/electrical interconnect architectures
- Experience with TSMC 7nm-2nm
- Strong analytical thinking and problem-solving skills
- Strong written and verbal communication skills
Benefits For High Speed SerDes RTL Design Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Annual discretionary bonus
- Equity awards
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