This position is part of a highly skilled multi-geographical team tasked with the development of high speed analog, mixed-signal IPs covering HBM, UCIe, PLL, and many others areas using the latest 5nm and 3nm FinFET technology. The team will be developing key differentiating IPs used in the Artificial Intelligence, Machine Learning, High Performance Computing and Hyper-Scale Data Center markets. Each member of the team is expected to be committed to the team success, create new innovation, and ensure customer usage satisfaction with first time right quality mindset.
Responsibilities include layout and verification of circuits to be used as part of state-of-the-art integrated circuits including PLLs, Phase Interpolators, high speed clock distribution networks, Rx Decision-Feedback Equalizers and deserializers, TX drivers and serializers, and High Speed DACs and ADCs.
The role involves developing detailed layout and performing all necessary verifications, as well as optimizing layout of circuits for power, performance, and integration to higher level IP / SOCs.
The ideal candidate will have wide-ranging experience, with a demonstrated ability to rely on both thorough understanding of layout fundamentals and creativity to solve circuit layout issues and problems.
Broadcom offers a competitive and comprehensive benefits package including medical, dental and vision plans, 401(K) participation with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
Broadcom is proud to be an equal opportunity employer and considers qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by law.