ASIC DESIGN FOR TEST ENGINEER - Acacia
Description For ASIC DESIGN FOR TEST ENGINEER - Acacia
Cisco's Acacia division is seeking an experienced ASIC Design for Test Engineer to join their team in Maynard, Massachusetts. This role is crucial in developing intelligent transceivers for high-speed fiber optic transmission markets, including data center, metro, and long-haul telecommunications networks.
As a member of the ASIC team's Design for Test group, you'll be responsible for implementing various testing methodologies including MBIST, REPAIR, Boundary Scan, and SCAN at both chip and block levels. The position requires deep expertise in ASIC DFT flows and implementation, with a focus on scan control logic, ATPG techniques, and post-silicon DVT.
The ideal candidate should have at least 8 years of experience with a BSEE (or equivalent experience with advanced degrees) and strong background in Synopsys/Mentor DFT tools. You'll work collaboratively with other DFT engineers and cross-functional teams to ensure successful tape outs.
Cisco offers an impressive benefits package including comprehensive health coverage, 401(k) matching, flexible time off, and paid volunteer time. The company is known for its inclusive culture and commitment to innovation in networking technology. This role offers an opportunity to work on cutting-edge technology while being part of a global leader in the networking industry.
The compensation range of $130,400 - $232,900 USD reflects the value Cisco places on experienced technical talent. Join a company that powers an inclusive future for all while working on advanced signal processing and photonic integration technologies.
Responsibilities For ASIC DESIGN FOR TEST ENGINEER - Acacia
- Set up and implement MBIST, REPAIR, Boundary Scan, EDT, OCC and SCAN at chip and/or block level
- Set up pattern generation flow for Scan/ATPG & MBIST/Repair/Fuse
- Work with seasoned DFT engineers to implement and verify DFT
- Interact with RTL/PD/STA/ATE teams for successful tape out
Requirements For ASIC DESIGN FOR TEST ENGINEER - Acacia
- BSEE or equivalent with +8 years of experience or MSEE with +6 years of experience, or PHD with +3 years of experience in ASIC DFT flows and Implementation
- Prior experience implementing scan control logic in RTL
- Prior experience with hierarchical ATPG and core wrapping techniques, ATPG and post-silicon DVT
- Prior experience with Synopsys/Mentor DFT tools
- TCL scripting experience to automate DFT flows
Benefits For ASIC DESIGN FOR TEST ENGINEER - Acacia
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company match
- Short and long-term disability coverage
- Basic life insurance
- Up to twelve paid holidays per year
- Vacation Time Off
- 80 hours of sick time off
- Paid time for volunteering
