ASIC Engineering Technical Leader

The Common Hardware Group (CHG) at Cisco delivers silicon, optics, and hardware platforms for core Switching, Routing, and Wireless products. As an ASIC Implementation Technical Lead with a focus on Design-for-Test, you'll work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. You'll be part of the Silicon One development organization, crafting groundbreaking next-generation networking chips.

Key responsibilities include:

• Developing test benches to verify comprehensive Design-for-Test (DFT) architecture
• Collaborating with design/design-verification and PD teams
• Working on innovative Hardware DFT & test strategies
• Identifying DFT challenges and leading junior engineers
• Debugging with minimal mentorship

The role requires a Bachelor's or Master's Degree in Electrical or Computer Engineering with at least 7 years of experience. You should have expertise in DFT, test and silicon engineering, Jtag protocols, Scan and BIST architectures, hardware design specifications, and various pre-silicon and post-silicon validation processes.

Cisco offers a collaborative work environment, competitive compensation, and comprehensive benefits. Join #WeAreCisco and be part of a team that embraces diversity, innovation, and makes a difference in the world of technology.