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ASIC Engineering Technical Leader

Cisco is the worldwide leader in technology that powers the internet, delivering networking hardware, software, and telecommunications equipment.
$184,000 - $266,000
Embedded
Staff Software Engineer
In-Person
5,000+ Employees
10+ years of experience
Enterprise SaaS · Networking
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Description For ASIC Engineering Technical Leader

Cisco, the worldwide leader in networking technology, is seeking an ASIC Engineering Technical Leader to join their Common Hardware Group (CHG). This role is integral to the development of Cisco Silicon One, the industry's only unifying silicon architecture that powers everything from top-of-rack switches to webscale data centers.

The position offers an opportunity to work on some of the most complex ASICs in the industry, focusing specifically on Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) methodology. As a technical leader, you'll be responsible for designing and implementing robust RTL solutions, managing comprehensive check flows, and ensuring the prevention of static glitch hazards.

The role combines deep technical expertise with leadership responsibilities, requiring both hands-on engineering work and strategic oversight. You'll be working with cutting-edge technology that enables Cisco's core Switching, Routing, and Wireless products, serving enterprises and service providers worldwide.

Cisco offers a comprehensive benefits package including medical, dental, and vision insurance, a 401(k) with company match, and flexible time off policies. The company culture strongly emphasizes work-life balance, professional development, and giving back to the community through paid volunteer time.

The position is based in San Jose, California, at the heart of Silicon Valley, offering competitive compensation between $184,000 and $266,000 USD. This is an excellent opportunity for an experienced ASIC engineer looking to take on a leadership role in a company that's shaping the future of networking technology.

The ideal candidate will bring at least 10 years of ASIC chip design experience, strong expertise in RTL development and asynchronous design, and a proven track record with CDC/RDC methodologies. If you're passionate about pushing the boundaries of silicon technology and leading technical initiatives in a collaborative environment, this role offers the perfect platform to make a significant impact in the networking industry.

Last updated a month ago

Responsibilities For ASIC Engineering Technical Leader

  • Leading the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips
  • Design & implement robust and reusable RTL with CDC/RDC considerations
  • Spec comprehensive CDC/RDC check flows and work with CAD team to implement
  • Review and approve CDC/RDC constraints and waivers
  • Perform static glitch analysis
  • Improve design with prevention of static glitch hazard

Requirements For ASIC Engineering Technical Leader

  • Bachelor's or Master's degree in Electrical Engineering
  • 10+ years of experience in ASIC chip design
  • Prior experience with RTL development on Asynchronous design
  • Prior experience on CDC/RDC concepts and relevant design implementation
  • Prior experience on maintaining CDC/RDC flow and signing-off constraints and waivers
  • Prior work with static glitch hazards and experience on relevant analysis on synthesis optimized gate netlists

Benefits For ASIC Engineering Technical Leader

401k
Medical Insurance
Dental Insurance
Vision Insurance
  • Medical insurance
  • Dental insurance
  • Vision insurance
  • 401(k) with company match
  • Short and long-term disability coverage
  • Basic life insurance
  • Up to 12 paid holidays per year
  • Birthday day off
  • Flexible Vacation Time Off policy
  • 80 hours of sick time off
  • Paid volunteer time
  • Performance-based incentive pay for sales roles

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